RING COUNTER(VERILOG CODE WITH TEST BENCH)

 4 BIT_RING UP/DOWN COUNTER:

            In this method, we determine the output with control input. When the control input is high,binary values getting shifted right. Function of the ring counter is to shift the value right/left. It is also called shift register,when the clock pulse is high D-flipflop get triggered.

 

 RING COUNTER 

 

 

 

 VERILOG CODE:

 

module ring(out,clk,res);
  input c,clk,res;
  output reg[3:0]out;
  reg [3:0]i;
  always@(posedge clk or posedge res)
    if(res)
      begin
        i=4'b0001;
      end
  else if(c)
    begin
      i<=i<<1;
      i[0]<=i[3];
    end
  else
    begin
      i<=i>>1;
      i[3]<=i[0];
    end
  assign out=i;
endmodule

 

       TEST BENCH:

 

module test;
  reg clk,res;
  wire [3:0]out;
  ring g(out,clk,res);
  initial begin
    clk=0;res=1;
    #1 res=0;
    #200
    $finish;
  end
  always #5 clk=~clk;
  initial begin
    $dumpfile("d.vcd");
    $dumpvars;
  end
endmodule